Reducing Power Loss, Cost and Complexity of SoC Power Delivery Using Integrated 3-Level Voltage Regulators
Traditional methods of system-on-chip (SoC) power management based on dynamic voltage and frequency scaling (DVFS) is limited by 1) cores/IP blocks sharing a voltage domain provided by off-chip voltage regulators (VR) and 2) slow voltage scaling time \((<0.1V/\mu s)\). This global, slow DVFS cann...
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| Language: | en_US |
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Harvard University
2013
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| Online Access: | http://dissertations.umi.com/gsas.harvard:10721 http://nrs.harvard.edu/urn-3:HUL.InstRepos:10423839 |