Soft Error Event Monte Carlo Modeling and Simulation: Impacts of Soft Error Events on Computer Memory

• Other Authors: Ogden, Christopher (authoraut)
• Format: Others
• Language: English; English
• Published: Florida State University
• Subjects: Computer science; Computer engineering
• Online Access: http://purl.flvc.org/fsu/fd/FSU_2016SU_Ogden_fsu_0071E_13415

This dissertation addresses the creation of a unique, adaptable, and light-weight core methodology to address the problem of Soft Error Modeling and Simulation. This core methodology was successfully tailored, validated, and expanded to work with a diverse cross-section of realistic memory devices, reliability techniques, and soft error event behaviors. These devices were shielded by a mutually supporting trio of reliability techniques while under the threat of soft error events. The techniques included in this dissertation are: (1) error correction codes, (2) interleaving distance, and (3) scrubbing. The strike-times, soft error event types, and bit error severities of the Soft Error Events were stochastically estimated using publicly available research findings published from a variety of proprietary reliability data sources. This proprietary data was gathered from certain secret vendor-specific computer memory devices. Both logically-oriented and physically-oriented memory cell organizational perspectives were incorporated into the core-methodology that was tailored to create the Simulators implemented within this dissertation. The failure probabilities of memory devices were calculated by the simulators that were designed and implemented within this dissertation. The results of these simulations were validated for specific test cases against the published literature models. This core methodology was applied to create scalable Simulators that were implemented utilizing a variety of soft error event behavioral characteristics, memory device design constraints, and reliability technique parameters. This core methodology and the simulators created from its application may be utilized by researchers to address a variety of open research questions in the field. An open research question was answered within this dissertation as proof of the effectiveness of the core methodology. This particular research question concerned establishing the significance of Soft Error Event (SEE) topography by studying the impact of Topographically reflective SEEs on the overall failure probability and corresponding reliability of the simulated memory device over time. To address this open research question, the Topographic 2-Parameter Weibull Soft Error (T2P-WSE) Simulator stochastically estimates the topographic strike-patterns of SEE severities based on the most commonly encountered Multiple Cell Upset shapes gathered by a commercial grade 3D-TCAD-based Neutron Particle Strike Simulation in a generic 45 nm SRAM (Static Random Access Memory) memory device. Both the failure probability and reliability results generated by the Topographic 2-Parameter Weibull Soft Error (T2P-WSE) Simulator were shown to be significantly different from the Row-Depth-Only 2-Parameter Weibull Soft Error Simulator (S2P-WSE) when given equivalent inputs. As documented within this dissertation, this conclusion was verified and confirmed from both a visual and statistical standpoint. Topography was observed to play a significant role in the overall failure probability of the device. It was concluded that the failure probability of the T2P-WSE Simulator was significantly reduced in comparison to the failure probability of the S2P-WSE Simulator. As defined for a variety of input parameters, the S2P-WSE Simulator consistently over-estimated the failure probability of the device. The reason for this outcome is directly related to the row-depth-only bit error severity assumption of the S2P-WSE Simulator. The row-depth-only assumption forces every MCU SEE impacts the device to spread its bit errors in a fixed row-depth-only pattern as opposed to a more realistic topographic pattern incorporated such as the patterns encoded into the T2P-WSE Simulator for the 45 nm memory chip geometry. This conclusion only served to reinforce the initial observation that when taking into account the spread of the bit errors, one would significantly reduce the overall failure probability for a memory storage device implemented with an interleaving distance architecture by taking into account its topographic shape. The core methodology calls for the stochastic estimation of the strike-time, type, and bit-error severity that represent all simulated soft error events destined to impact the simulated device at some simulation time unit over the total simulation run-time. These Soft Error Events will strike the device at the appointed strike-time and be mitigated by the chosen set of mutually supporting reliability techniques. These reliability techniques include the following: (1) error correcting codes, (2) interleaving distance, and (3) scrubbing. This core methodology was fitted to the Compound Poisson and a logical memory cell organization for the Compound Poisson Soft Error Simulator. This core methodology was also successfully applied to the 2 Parameter Weibull Failure Distribution and a Physical Memory Cell organization. Both CPSE and S2P-WSE Simulators proved equally capable in calculating the failure probability of any variety of simulated memory storage devices shielded by the three integrated reliability techniques under the Impact of these stochastically determined soft error events. This failure probability over simulated time was utilized to evaluate all of the secondary results of the Core Methodology including such results as the Mean-Time-To Failure and Failures-In-Time Number at the conclusion of each simulation run. All of the simulators presented within this dissertation were implemented within a Matlab programming environment. === A Dissertation submitted to the Department of Computer Science in partial fulfillment of the requirements for the degree of Doctor of Philosophy. === Summer Semester 2016. === July 12, 2016. === Compound Poisson, Computer Memory, Reliability, Soft Errors, Stochastic Simulation, Weibull Distribution === Includes bibliographical references. === Michael Mascagni, Professor Directing Dissertation; Dennis Duke, University Representative; Robert van Engelen, Committee Member; Piyush Kumar, Committee Member.