Synthesizable SystemC to VHDL Compiler Design
Efficient hardware/software codesign framework will greatly facilitate not only the design but also the verification early in the embedded system deign cycle. With these electric design automation (EDA) tools, the hardware can be concisely modeled at a higher abstraction level better than with the m...
Other Authors: | Chen, Rui (authoraut) |
---|---|
Format: | Others |
Language: | English English |
Published: |
Florida State University
|
Subjects: | |
Online Access: | http://purl.flvc.org/fsu/fd/FSU_migr_etd-4767 |
Similar Items
-
A Synthesizable VHDL Model of the Serial Communication Interface and Synchronous Serial Interface of Motorola DSP56002
by: Mattam, Swaroop
Published: (2006) -
Multipurpose synthesizable SystemVerilog Spi-Bus protocol verification system
by: Raappana, M. (Markku)
Published: (2017) -
Hardware modeling and top-down design using VHDL
by: Morton, Dennis P. (Dennis Paul)
Published: (2008) -
Dynamic Assertion-Based Verification for SystemC
Published: (2013) -
Behavioral simulation and synthesis of biological neuron systems using synthesizable VHDL
by: Bailey, J.A, et al.
Published: (2011)