Fast transient LDO using digital detection.

• Other Authors: Kwong, Ka Yee.
• Format: Others
• Language: English; Chinese
• Published: 2012
• Subjects: Voltage regulators; Field-effect transistors; Low voltage integrated circuits > Design and construction
• Online Access: http://library.cuhk.edu.hk/record=b5549104; http://repository.lib.cuhk.edu.hk/en/item/cuhk-328753

電源管理集成電路被廣泛應用於便攜式電子應用。在同一芯片需要不同的電源電壓水平。由於芯片尺寸，工作速度和所需功耗的要求，低壓差穩壓器（LDO）在快遞瞬態響應，低噪聲，以及高精度的電子產品中具有廣泛的應用。 === LDO的負載瞬間變化取決於功率金氧半場效電晶體的大小、偏置電流和誤差放大器的增益。檢測輸出電壓，並使用大電容和電阻通過電容耦合，增加偏置電流是一個簡單的方法來改善負載瞬間變化。然而，電阻電容佔據較大的芯片面積。 === 權衡功耗和芯片尺寸，本論文中提出用數字檢測電路取代用於瞬態耦合的大電容和電阻。所提出的電路是讓功率金氧半場效電晶體的栅極電容電流增加充電或放電，以提高LDO的負載瞬間響應速度。產生這種電流通過檢測內部的變化，並產生一個電壓脈衝控制迴轉電流，然後通過使用一組數字電路去改變充電或放電的電量。 === 擬議的設計已在UMC0.18微米 CMOS制程技術實現。LDO的輸入電壓為0.9伏至1.3伏和穩壓0.7伏。最大輸出電流為50豪安。經過測量，負載瞬間變化得到改善。負載瞬間的響應時間可以從75微秒（傳統）減少到75納秒。 === Power-management IC is widely used in portable electronic applications. Different supply voltage levels are required in the same chip. Due to the size, speed and power requirements, low-dropout regulator (LDO) is generally adopted for applications which need fast transient response, low noise and high accuracy. === Transient response of a LDO is limited by the size of power MOSFET, biasing current and gain of error amplifier. Detecting the output voltage and using large RC components for capacitive coupling to increase the biasing current is a straightforward method to improve the transient response. However, this requires a large chip size for the RC components. === By considering power consumption and size, digital detection circuit is proposed to replace the large capacitors and resistors used for transient coupling. The proposed circuit is to increase the charging or discharging current to the gate of the power MOSFET to increase the transient speed of LDO. This current is generated by detecting the internal changes and generating a voltage pulse to control the slewing current by using a set of digital circuit. === The proposed design has been realized in UMC 0.18μm CMOS technology. The input voltage of the LDO is 0.9 to 1.3V and the regulated voltage is 0.7V. The maximum output current is 50mA. From the measurement, the transient response is improved. The response time due to load transient changes can be reduced from 75s (conventional) to 75ns. === Detailed summary in vernacular field only. === Detailed summary in vernacular field only. === Detailed summary in vernacular field only. === Detailed summary in vernacular field only. === Kwong, Ka Yee. === Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. === Includes bibliographical references. === Abstracts also in Chinese. === Abstract === Acknowledgments === Table of Content === List of Figures === List of Tables === Chapter Chapter 1 --- LDO regulator research background === Introduction === Chapter Section 1.1 --- Generic LDO regulator structure === Chapter Section 1.2 --- Principle of LDO regulator operation === Chapter Section 1.3 --- Specifications === Chapter References === Chapter Chapter 2 --- Review of state-of-the-art transient-improvement techniques for LDO regulators === Introduction === Chapter Section 2.1 --- Slew rate improvement at power transistor gate === Chapter Section 2.2 --- Frequency compensation === Chapter Section 2.3 --- Short summary === References === Chapter Chapter 3 --- A proposed output-capacitorless LDO regulator with digital voltage spike detection === Chapter Introduction === Chapter Section 3.1 --- LDO regulator core structure === Chapter Section 3.2 --- Digital switches based LDO regulator === Chapter Section 3.3 --- LDO regulator with proposed digital voltage spike detection circuit === Chapter Section 3.4 --- Simulation result === Chapter Section 3.5 --- Short summary === References === Chapter Chapter 4 --- Measurement results === Introduction === Chapter Chapter 5 --- Conclusion and Future Work