Clock routing for high performance microprocessor designs.

• Other Authors: Tian, Haitong.
• Format: Others
• Language: English; Chinese
• Published: 2011
• Subjects: Microprocessors > Design and construction; Integrated circuits > Very large scale integration; Timing circuits > Design and construction
• Online Access: http://library.cuhk.edu.hk/record=b5894819; http://repository.lib.cuhk.edu.hk/en/item/cuhk-327550

Tian, Haitong. === Chinese abstract is on unnumbered page. === Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. === Includes bibliographical references (p. 65-74). === Abstracts in English and Chinese. === Abstract --- p.i === Acknowledgement --- p.iii === Chapter 1 --- Introduction --- p.1 === Chapter 1.1 --- Motivations --- p.1 === Chapter 1.2 --- Our Contributions --- p.2 === Chapter 1.3 --- Organization of the Thesis --- p.3 === Chapter 2 --- Background Study --- p.4 === Chapter 2.1 --- Traditional Clock Routing Problem --- p.4 === Chapter 2.2 --- Tree-Based Clock Routing Algorithms --- p.5 === Chapter 2.2.1 --- Clock Routing Using H-tree --- p.5 === Chapter 2.2.2 --- Method of Means and Medians(MMM) --- p.6 === Chapter 2.2.3 --- Geometric Matching Algorithm (GMA) --- p.8 === Chapter 2.2.4 --- Exact Zero-Skew Algorithm --- p.9 === Chapter 2.2.5 --- Deferred Merge Embedding (DME) --- p.10 === Chapter 2.2.6 --- Boundary Merging and Embedding (BME) Algorithm --- p.14 === Chapter 2.2.7 --- Planar Clock Routing Algorithm --- p.17 === Chapter 2.2.8 --- Useful-skew Tree Algorithm --- p.18 === Chapter 2.3 --- Non-Tree Clock Distribution Networks --- p.19 === Chapter 2.3.1 --- Grid (Mesh) Structure --- p.20 === Chapter 2.3.2 --- Spine Structure --- p.20 === Chapter 2.3.3 --- Hybrid Structure --- p.21 === Chapter 2.4 --- Post-grid Clock Routing Problem --- p.22 === Chapter 2.5 --- Limitations of the Previous Work --- p.24 === Chapter 3 --- Post-Grid Clock Routing Problem --- p.26 === Chapter 3.1 --- Introduction --- p.26 === Chapter 3.2 --- Problem Definition --- p.27 === Chapter 3.3 --- Our Approach --- p.30 === Chapter 3.3.1 --- Delay-driven Path Expansion Algorithm --- p.31 === Chapter 3.3.2 --- Pre-processing to Connect Critical ports --- p.34 === Chapter 3.3.3 --- Post-processing to Reduce Capacitance --- p.36 === Chapter 3.4 --- Experimental Results --- p.39 === Chapter 3.4.1 --- Experiment Setup --- p.39 === Chapter 3.4.2 --- Validations of the Delay and Slew Estimation --- p.39 === Chapter 3.4.3 --- Comparisons with the Tree Grow (TG) Approach --- p.41 === Chapter 3.4.4 --- Lowest Achievable Delays --- p.42 === Chapter 3.4.5 --- Simulation Results --- p.42 === Chapter 4 --- Non-tree Based Post-Grid Clock Routing Problem --- p.44 === Chapter 4.1 --- Introduction --- p.44 === Chapter 4.2 --- Handling Ports with Large Load Capacitances --- p.46 === Chapter 4.2.1 --- Problem Ports Identification --- p.47 === Chapter 4.2.2 --- Non-Tree Construction --- p.47 === Chapter 4.2.3 --- Wire Link Selection --- p.48 === Chapter 4.3 --- Path Expansion in Non-tree Algorithm --- p.51 === Chapter 4.4 --- Limitations of the Non-tree Algorithm --- p.51 === Chapter 4.5 --- Experimental Results --- p.51 === Chapter 4.5.1 --- Experiment Setup --- p.51 === Chapter 4.5.2 --- Validations of the Delay and Slew Estimation --- p.52 === Chapter 4.5.3 --- Lowest Achievable Delays --- p.53 === Chapter 4.5.4 --- Results on New Benchmarks --- p.53 === Chapter 4.5.5 --- Simulation Results --- p.55 === Chapter 5 --- Efficient Partitioning-based Extension --- p.57 === Chapter 5.1 --- Introduction --- p.57 === Chapter 5.2 --- Partition-based Extension --- p.58 === Chapter 5.3 --- Experimental Results --- p.61 === Chapter 5.3.1 --- Experiment Setup --- p.61 === Chapter 5.3.2 --- Running Time Improvement with Partitioning Technique --- p.61 === Chapter 6 --- Conclusion --- p.63 === Bibliography --- p.65