On FPGA implementations for bioinformatics, neural prosthetics and reinforcement learning problems.

• Other Authors: Mak, Sui Tung Terrence.
• Format: Others
• Language: English; Chinese
• Published: 2005
• Subjects: Field programmable gate arrays > Design and construction; Bioinformatics; Neurons > Computer simulation; Prosthesis; Reinforcement learning
• Online Access: http://library.cuhk.edu.hk/record=b5892709; http://repository.lib.cuhk.edu.hk/en/item/cuhk-325275

Mak Sui Tung Terrence. === Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. === Includes bibliographical references (leaves 132-142). === Abstracts in English and Chinese. === Abstract --- p.i === List of Tables --- p.iv === List of Figures --- p.v === Acknowledgements --- p.ix === Chapter 1. --- Introduction --- p.1 === Chapter 1.1 --- Bioinformatics --- p.1 === Chapter 1.2 --- Neural Prosthetics --- p.4 === Chapter 1.3 --- Learning in Uncertainty --- p.5 === Chapter 1.4 --- The Field Programmable Gate Array (FPGAs) --- p.7 === Chapter 1.5 --- Scope of the Thesis --- p.10 === Chapter 2. --- A Hybrid GA-DP Approach for Searching Equivalence Sets --- p.14 === Chapter 2.1 --- Introduction --- p.16 === Chapter 2.2 --- Equivalence Set Criterion --- p.18 === Chapter 2.3 --- Genetic Algorithm and Dynamic Programming --- p.19 === Chapter 2.3.1 --- Genetic Algorithm Formulation --- p.20 === Chapter 2.3.2 --- Bounded Mutation --- p.21 === Chapter 2.3.3 --- Conditioned Crossover --- p.22 === Chapter 2.3.4 --- Implementation --- p.22 === Chapter 2.4 --- FPGAs Implementation of GA-DP --- p.24 === Chapter 2.4.1 --- System Overview --- p.25 === Chapter 2.4.2 --- Parallel Computation for Transitive Closure --- p.26 === Chapter 2.4.3 --- Genetic Operation Realization --- p.28 === Chapter 2.5 --- Discussion --- p.30 === Chapter 2.6 --- Limitation and Future Work --- p.33 === Chapter 2.7 --- Conclusion --- p.34 === Chapter 3. --- An FPGA-based Architecture for Maximum-Likelihood Phylogeny Evaluation --- p.35 === Chapter 3.1 --- Introduction --- p.36 === Chapter 3.2 --- Maximum-Likelihood Model --- p.39 === Chapter 3.3 --- Hardware Mapping for Pruning Algorithm --- p.41 === Chapter 3.3.1 --- Related Works --- p.41 === Chapter 3.3.2 --- Number Representation --- p.42 === Chapter 3.3.3 --- Binary Tree Representation --- p.43 === Chapter 3.3.4 --- Binary Tree Traversal --- p.45 === Chapter 3.3.5 --- Maximum-Likelihood Evaluation Algorithm --- p.46 === Chapter 3.4 --- System Architecture --- p.49 === Chapter 3.4.1 --- Transition Probability Unit --- p.50 === Chapter 3.4.2 --- State-Parallel Computation Unit --- p.51 === Chapter 3.4.3 --- Error Computation --- p.54 === Chapter 3.5 --- Discussion --- p.56 === Chapter 3.5.1 --- Hardware Resource Consumption --- p.56 === Chapter 3.5.2 --- Delay Evaluation --- p.57 === Chapter 3.6 --- Conclusion --- p.59 === Chapter 4. --- Field Programmable Gate Array Implementation of Neuronal Ion Channel Dynamics --- p.61 === Chapter 4.1 --- Introduction --- p.62 === Chapter 4.2 --- Background --- p.63 === Chapter 4.2.1 --- Analog VLSI Model for Hebbian Synapse --- p.63 === Chapter 4.2.2 --- A Unifying Model of Bi-directional Synaptic Plasticity --- p.64 === Chapter 4.2.3 --- Non-NMDA Receptor Channel Regulation --- p.65 === Chapter 4.3 --- FPGAs Implementation --- p.65 === Chapter 4.3.1 --- FPGA Design Flow --- p.65 === Chapter 4.3.2 --- Digital Model of NMD A and AMPA receptors --- p.65 === Chapter 4.3.3 --- Synapse Modification --- p.67 === Chapter 4.4 --- Results --- p.68 === Chapter 4.4.1 --- Simulation Results --- p.68 === Chapter 4.5 --- Discussion --- p.70 === Chapter 4.6 --- Conclusion --- p.71 === Chapter 5. --- Continuous-Time and Discrete-Time Inference Networks for Distributed Dynamic Programming --- p.72 === Chapter 5.1 --- Introduction --- p.74 === Chapter 5.2 --- Background --- p.77 === Chapter 5.2.1 --- Markov decision process (MDPs) --- p.78 === Chapter 5.2.2 --- Learning in the MDPs --- p.80 === Chapter 5.2.3 --- Bellman Optimal Criterion --- p.80 === Chapter 5.2.4 --- Value Iteration --- p.81 === Chapter 5.3 --- A Computational Framework for Continuous-Time Inference Network --- p.82 === Chapter 5.3.1 --- Binary Relation Inference Network --- p.83 === Chapter 5.3.2 --- Binary Relation Inference Network for MDPs --- p.85 === Chapter 5.3.3 --- Continuous-Time Inference Network for MDPs --- p.87 === Chapter 5.4 --- Convergence Consideration --- p.88 === Chapter 5.5 --- Numerical Simulation --- p.90 === Chapter 5.5.1 --- Example 1: Random Walk --- p.90 === Chapter 5.5.2 --- Example 2: Random Walk on a Grid --- p.94 === Chapter 5.5.3 --- Example 3: Stochastic Shortest Path Problem --- p.97 === Chapter 5.5.4 --- Relationships Between λ and γ --- p.99 === Chapter 5.6 --- Discrete-Time Inference Network --- p.100 === Chapter 5.6.1 --- Results --- p.101 === Chapter 5.7 --- Conclusion --- p.102 === Chapter 6. --- On Distributed g-Learning Network --- p.104 === Chapter 6.1 --- Introduction --- p.105 === Chapter 6.2 --- Distributed Q-Learniing Network --- p.108 === Chapter 6.2.1 --- Distributed Q-Learning Network --- p.109 === Chapter 6.2.2 --- Q-Learning Network Architecture --- p.111 === Chapter 6.3 --- Experimental Results --- p.114 === Chapter 6.3.1 --- Random Walk --- p.114 === Chapter 6.3.2 --- The Shortest Path Problem --- p.116 === Chapter 6.4 --- Discussion --- p.120 === Chapter 6.4.1 --- Related Work --- p.121 === Chapter 6.5 --- FPGAs Implementation --- p.122 === Chapter 6.5.1 --- Distributed Registering Approach --- p.123 === Chapter 6.5.2 --- Serial BRAM Storing Approach --- p.124 === Chapter 6.5.3 --- Comparison --- p.125 === Chapter 6.5.4 --- Discussion --- p.127 === Chapter 6.6 --- Conclusion --- p.128 === Chapter 7. --- Summary --- p.129 === Bibliography --- p.132 === Appendix === Chapter A. --- Simplified Floating-Point Arithmetic --- p.143 === Chapter B. --- "Logarithm, Exponential and Division Implementation" --- p.144 === Chapter B.1 --- Introduction --- p.144 === Chapter B.2 --- Approximation Scheme --- p.145 === Chapter B.2.1 --- Logarithm --- p.145 === Chapter B.2.2 --- Exponentiation --- p.147 === Chapter B.2.3 --- Division --- p.148 === Chapter C. --- Analog VLSI Implementation --- p.150 === Chapter C.1 --- Site Function --- p.150 === Chapter C.1.1 --- Multiplication Cell --- p.150 === Chapter C.2 --- The Unit Function --- p.153 === Chapter C.3 --- The Inference Network Computation --- p.154 === Chapter C.4 --- Layout --- p.157 === Chapter C.5 --- Fabrication --- p.159 === Chapter C.5.1 --- Testing and Characterization --- p.161