Efficient alternative wiring techniques and applications.
Sze, Chin Ngai. === Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. === Includes bibliographical references (leaves 80-84) and index. === Abstracts in English and Chinese. === Abstract --- p.i === Acknowledgments --- p.iii === Curriculum Vitae --- p.iv === List of Figures --- p.ix === L...
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Format: | Others |
Language: | English Chinese |
Published: |
2001
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Online Access: | http://library.cuhk.edu.hk/record=b5890816 http://repository.lib.cuhk.edu.hk/en/item/cuhk-323566 |
Summary: | Sze, Chin Ngai. === Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. === Includes bibliographical references (leaves 80-84) and index. === Abstracts in English and Chinese. === Abstract --- p.i === Acknowledgments --- p.iii === Curriculum Vitae --- p.iv === List of Figures --- p.ix === List of Tables --- p.xii === Chapter 1 --- Introduction --- p.1 === Chapter 1.1 --- Motivation and Aims --- p.1 === Chapter 1.2 --- Contribution --- p.8 === Chapter 1.3 --- Organization of Dissertation --- p.10 === Chapter 2 --- Definitions and Notations --- p.11 === Chapter 3 --- Literature Review --- p.15 === Chapter 3.1 --- Logic Reconstruction --- p.15 === Chapter 3.1.1 --- SIS: A System for Sequential and Combinational Logic Synthesis --- p.16 === Chapter 3.2 --- ATPG-based Alternative Wiring --- p.17 === Chapter 3.2.1 --- Redundancy Addition and Removal for Logic Optimization --- p.18 === Chapter 3.2.2 --- Perturb and Simplify Logic Optimization --- p.18 === Chapter 3.2.3 --- REWIRE --- p.21 === Chapter 3.2.4 --- Implication-tree Based Alternative Wiring Logic Trans- formation --- p.22 === Chapter 3.3 --- Graph-based Alternative Wiring --- p.24 === Chapter 4 --- Implication Based Alternative Wiring Logic Transformation --- p.25 === Chapter 4.1 --- Source Node Implication --- p.25 === Chapter 4.1.1 --- Introduction --- p.25 === Chapter 4.1.2 --- Implication Relationship and Implication-tree --- p.25 === Chapter 4.1.3 --- Selection of Alternative Wire Based on Implication-tree --- p.29 === Chapter 4.1.4 --- Implication-tree Based Logic Transformation --- p.32 === Chapter 4.2 --- Destination Node Implication --- p.35 === Chapter 4.2.1 --- Introduction --- p.35 === Chapter 4.2.2 --- Destination Node Relationship --- p.35 === Chapter 4.2.3 --- Destination Node Implication-tree --- p.39 === Chapter 4.2.4 --- Selection of Alternative Wire --- p.41 === Chapter 4.3 --- The Algorithm --- p.43 === Chapter 4.3.1 --- IB AW Implementation --- p.43 === Chapter 4.3.2 --- Experimental Results --- p.43 === Chapter 4.4 --- Conclusion --- p.45 === Chapter 5 --- Graph Based Alternative Wiring Logic Transformation --- p.47 === Chapter 5.1 --- Introduction --- p.47 === Chapter 5.2 --- Notations and Definitions --- p.48 === Chapter 5.3 --- Alternative Wire Patterns --- p.50 === Chapter 5.4 --- Construction of Minimal Patterns --- p.54 === Chapter 5.4.1 --- Minimality of Patterns --- p.54 === Chapter 5.4.2 --- Minimal Pattern Formation --- p.56 === Chapter 5.4.3 --- Pattern Extraction --- p.61 === Chapter 5.5 --- Experimental Results --- p.63 === Chapter 5.6 --- Conclusion --- p.63 === Chapter 6 --- Logic Optimization by GBAW --- p.66 === Chapter 6.1 --- Introduction --- p.66 === Chapter 6.2 --- Logic Simplification --- p.67 === Chapter 6.2.1 --- Single-Addition-Multiple-Removal by Pattern Feature . . --- p.67 === Chapter 6.2.2 --- Single-Addition-Multiple-Removal by Combination of Pat- terns --- p.68 === Chapter 6.2.3 --- Single-Addition-Single-Removal --- p.70 === Chapter 6.3 --- Incremental Perturbation Heuristic --- p.71 === Chapter 6.4 --- GBAW Optimization Algorithm --- p.73 === Chapter 6.5 --- Experimental Results --- p.73 === Chapter 6.6 --- Conclusion --- p.76 === Chapter 7 --- Conclusion --- p.78 === Bibliography --- p.80 === Chapter A --- VLSI Design Cycle --- p.85 === Chapter B --- Alternative Wire Patterns in [WLFOO] --- p.87 === Chapter B.1 --- 0-local Pattern --- p.87 === Chapter B.2 --- 1-local Pattern --- p.88 === Chapter B.3 --- 2-local Pattern --- p.89 === Chapter B.4 --- Fanout-reconvergent Pattern --- p.90 === Chapter C --- New Alternative Wire Patterns --- p.91 === Chapter C.1 --- Pattern Cluster C1 --- p.91 === Chapter C.1.1 --- NAND-NAND-AND/NAND;AND/NAND --- p.91 === Chapter C.1.2 --- NOR-NOR-OR/NOR;AND/NAND --- p.92 === Chapter C.1.3 --- AND-NOR-OR/NOR;OR/NOR --- p.95 === Chapter C.1.4 --- OR-NAND-AND/NAND;AND/NAND --- p.95 === Chapter C.2 --- Pattern Cluster C2 --- p.98 === Chapter C.3 --- Pattern Cluster C3 --- p.99 === Chapter C.4 --- Pattern Cluster C4 --- p.104 === Chapter C.5 --- Pattern Cluster C5 --- p.105 === Glossary --- p.106 === Index --- p.108 |
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