Replacement and placement policies for prefetched lines.

• Other Authors: Sze, Siu Ching.
• Format: Others
• Language: English
• Published: 1998
• Subjects: Cache memory; Memory management (Computer science); Random access memory
• Online Access: http://library.cuhk.edu.hk/record=b5889618; http://repository.lib.cuhk.edu.hk/en/item/cuhk-322182

by Sze Siu Ching. === Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. === Includes bibliographical references (leaves 119-122). === Chapter 1 --- Introduction --- p.1 === Chapter 1.1 --- Overlapping Computations with Memory Accesses --- p.3 === Chapter 1.2 --- Cache Line Replacement Policies --- p.4 === Chapter 1.3 --- The Rest of This Paper --- p.4 === Chapter 2 --- A Brief Review of IAP Scheme --- p.6 === Chapter 2.1 --- Embedded Hints for Next Data References --- p.6 === Chapter 2.2 --- Instruction Opcode and Addressing Mode Prefetching --- p.8 === Chapter 2.3 --- Chapter Summary --- p.9 === Chapter 3 --- Motivation --- p.11 === Chapter 3.1 --- Chapter Summary --- p.14 === Chapter 4 --- Related Work --- p.15 === Chapter 4.1 --- Existing Replacement Algorithms --- p.16 === Chapter 4.2 --- Placement Policies for Cache Lines --- p.18 === Chapter 4.3 --- Chapter Summary --- p.20 === Chapter 5 --- Replacement and Placement Policies of Prefetched Lines --- p.21 === Chapter 5.1 --- IZ Cache Line Replacement Policy in IAP scheme --- p.22 === Chapter 5.1.1 --- The Instant Zero Scheme --- p.23 === Chapter 5.2 --- Priority Pre-Updating and Victim Cache --- p.27 === Chapter 5.2.1 --- Priority Pre-Updating --- p.27 === Chapter 5.2.2 --- Priority Pre-Updating for Cache --- p.28 === Chapter 5.2.3 --- Victim Cache for Unreferenced Prefetch Lines --- p.28 === Chapter 5.3 --- Prefetch Cache for IAP Lines --- p.31 === Chapter 5.4 --- Chapter Summary --- p.33 === Chapter 6 --- Performance Evaluation --- p.34 === Chapter 6.1 --- Methodology and metrics --- p.34 === Chapter 6.1.1 --- Trace Driven Simulation --- p.35 === Chapter 6.1.2 --- Caching Models --- p.36 === Chapter 6.1.3 --- Simulation Models and Performance Metrics --- p.39 === Chapter 6.2 --- Simulation Results --- p.43 === Chapter 6.2.1 --- General Results --- p.44 === Chapter 6.3 --- Simulation Results of IZ Replacement Policy --- p.49 === Chapter 6.3.1 --- Analysis To IZ Cache Line Replacement Policy --- p.50 === Chapter 6.4 --- Simulation Results for Priority Pre-Updating with Victim Cache --- p.52 === Chapter 6.4.1 --- PPUVC in Cache with IAP Scheme --- p.52 === Chapter 6.4.2 --- PPUVC in prefetch-on-miss Cache --- p.54 === Chapter 6.5 --- Prefetch Cache --- p.57 === Chapter 6.6 --- Chapter Summary --- p.63 === Chapter 7 --- Architecture Without LOAD-AND-STORE Instructions --- p.64 === Chapter 8 --- Conclusion --- p.66 === Chapter A --- CPI Due to Cache Misses --- p.68 === Chapter A.1 --- Varying Cache Size --- p.68 === Chapter A.1.1 --- Instant Zero Replacement Policy --- p.68 === Chapter A.1.2 --- Priority Pre-Updating with Victim Cache --- p.70 === Chapter A.1.3 --- Prefetch Cache --- p.73 === Chapter A.2 --- Varying Cache Line Size --- p.75 === Chapter A.2.1 --- Instant Zero Replacement Policy --- p.75 === Chapter A.2.2 --- Priority Pre-Updating with Victim Cache --- p.77 === Chapter A.2.3 --- Prefetch Cache --- p.80 === Chapter A.3 --- Varying Cache Set Associative --- p.82 === Chapter A.3.1 --- Instant Zero Replacement Policy --- p.82 === Chapter A.3.2 --- Priority Pre-Updating with Victim Cache --- p.84 === Chapter A.3.3 --- Prefetch Cache --- p.87 === Chapter B --- Simulation Results of IZ Replacement Policy --- p.89 === Chapter B.1 --- Memory Delay Time Reduction --- p.89 === Chapter B.1.1 --- Varying Cache Size --- p.89 === Chapter B.1.2 --- Varying Cache Line Size --- p.91 === Chapter B.1.3 --- Varying Cache Set Associative --- p.93 === Chapter C --- Simulation Results of Priority Pre-Updating with Victim Cache --- p.95 === Chapter C.1 --- PPUVC in IAP Scheme --- p.95 === Chapter C.1.1 --- Memory Delay Time Reduction --- p.95 === Chapter C.2 --- PPUVC in Cache with Prefetch-On-Miss Only --- p.101 === Chapter C.2.1 --- Memory Delay Time Reduction --- p.101 === Chapter D --- Simulation Results of Prefetch Cache --- p.107 === Chapter D.1 --- Memory Delay Time Reduction --- p.107 === Chapter D.1.1 --- Varying Cache Size --- p.107 === Chapter D.1.2 --- Varying Cache Line Size --- p.109 === Chapter D.1.3 --- Varying Cache Set Associative --- p.111 === Chapter D.2 --- Results of the Three Replacement Policies --- p.113 === Chapter D.2.1 --- Varying Cache Size --- p.113 === Chapter D.2.2 --- Varying Cache Line Size --- p.115 === Chapter D.2.3 --- Varying Cache Set Associative --- p.117 === Bibliography --- p.119