Embedded Systems for Photonic Cognitive Sensing

• Main Author: Gidony, David
• Language: English
• Published: 2019
• Subjects: Electrical engineering; Biomedical engineering; Optical communications; Photonics; Brain > Imaging
• Online Access: https://doi.org/10.7916/d8-w6wy-4v31

This research addresses challenges in two major applications, both related to photonic cognitive sensing. The first part, “Implantable Photonic Nano-Probe Detectors for Neural Imaging”, focuses on imaging system in the neural sciences field. The second part, “Advanced Control System for Optical Data Communications”, covers embedded low power control systems for optical communications. Implantable Photonic Nano-Probe Detectors for Neural Imaging This first part address the problem of simultaneous and real-time monitoring of dense brain neural activity, with the capability of cellular resolution and cell-type specificity included. For decades, electrophysiology has been the “gold standard” for the recording of neural activity. Despite recent advances, electrophysiology techniques can typically monitor fewer than 100 neurons simultaneously, due to the practical limits of electrode density. Additionally, the ability of direct monitoring specific cell types is not possible here. With the introduction of a growing panel of fluorescent optical reporters for brain function mapping, optical microscopy techniques have demonstrated the ability to track the activity of hundreds of neurons simultaneously in a much less invasive manner but with high spatial resolution, low-to-moderate temporal resolution and cell-type specificity. Unfortunately, only superficial layers of the brain can be imaged by free-space microscopy, due to the intrinsic light scattering and absorption limitation in brain tissue. To allow optical fluorescence imaging of deeper layers of the brain with proper a signal-to-noise ratio, a dense and scalable 3-D lattice of photo emitter and detector pixels (E-Pixels and D-Pixels, respectively) must be distributed on shanks for possible insertion into the brain. The 3-D lattice (combined fluorescent optical reporters) is expected to give an activity image of a very large neural population at an arbitrary depth in the brain. This work presents the design and implementation of the aforementioned 3-D photo- detectors (D-Pixels), associated with data processing and readout circuitries, for the future assembly of a probe-based system for functional imaging of neural activity. One of the main challenges of producing a probed-based version of a fluorescence microscope is the rejection of the light used to excite the fluorescent reporters. This is commonly done in the spectral domain with band-pass filters for free-space microscopy. However, these filters are not implementable with the proper optical density at the probe scale. The probe-based photo-detectors must be capable of rejecting the excitation light and capturing only the fluorescent response without the use of optical filters. Integrated Geiger-mode single-photon avalanche diodes (SPADs) are used as the sensing devices, which provide the ability to capture low fluorescence signals, fast response in the time domain, and direct digital readout. By engineering narrow E-Pixels angular-excitation fields and overlapping them with the narrow D-Pixels detection fields, fluorescent sources can be spatially localized. The detectors are embedded into four ultra-thin implantable shanks, associated with data processing units and readout circuits, all forming the photonic nano-probe detectors (also referred to as “D-Pixels Camera Chip (DCC)”). The shanks have dimensions of 110um×50um each, with 100 pixels along a shank (a total number of 400 pixels), distributed over 3mm length. The data generated by the photonic nano-probe detectors, is serially streamed out at a rate of 640Mbps, for offline analysis and image reconstruction. The photonic nano-probe detectors are fabricated in a conventional CMOS 0.13um technology. This part of the thesis first proposes and develops the architecture of the photonic nano-probe detectors. The challenges of designing high density, ultra-thin probes with the aforementioned form factor, fabricated in CMOS 0.13um technology is also discussed. Secondly, the design and implementation of testability and debugging options are mentioned, as playing an important role in achieving research goals. Last the design of lab experimental setups is presented and as well as the measurement results of the photonic nano-probe detectors. Experimental results indicate on achieving the crucial key features of the research work, the capability of rejecting the excitation light and capturing only the fluorescent decay response without the use of optical filters. Additionally, the results show that the photonic nano-probe detectors can precisely localize and map into a 2-D image, a light source within a pixel resolution.   Advanced Control System for Optical Data Communications The second part of the thesis focuses on the problem of initialization and temperature stabilization of silicon photonic (SiP) devices, with focus on dramatic power reduction of the power consumption. While microelectronics technology continues growing in scale, bandwidth, and integration of multiple systems on a single silicon die, the traditional electrical interconnects become the speed bottleneck in high-performance data communication systems. On the other hand, silicon photonics offers a promising platform for integration and manufacturing of photonics devices for high speed data transfer applications, such as access networks, supercomputers, chip-to-chip interconnects, and data centers. Additionally, the high index contrast of silicon platform and its compatibility with CMOS technologies, gives rise to integration of high speed, power efficient silicon photonic interconnects and most innovative CMOS technologies. Micro-ring resonators (MMRs), which are important building blocks is many silicon photonics applications, became attractive devices in many optical communication systems. This is due to their wavelength tuning ability, low power consumption and small footprint. However, temperature changes in their environment will shift their resonance from the desired point (due to high thermo-optical coupling in silicon), leading to performance degradation of the optical link. Compensating the degradation in performance can be directly translated to an excess in overall power consumption of the link, which will be critical in high-speed optical data communication systems. This work develops and demonstrates an ultra-low power control system, for initialization and temperature stabilization of MMRs. It utilizes an integrated heater, to thermally tune and lock the resonator to the desired wavelength. Traditional feedback loops rely on tapping a portion of the optical signal with the use of integrated photodiodes. They lock on the desired wavelength by sensing the maximum signal intensity, observed by the photodiode. The suggested control system in this work is based on an analog control system and utilizes the photo-conductance effect of doped-resistive heaters, to sense the optical power through the micro-ring. This part of the thesis first develops a VERILOG-A model for the photo-conductance effect of the doped-resistive heater. This enables the integration of the heater’s model with the proposed control circuits, into a circuit design simulator. Secondly, an architecture for the control system is proposed and developed, which includes fundamental electronic circuits with the aforementioned heater’s model. For the purpose of circuit level simulations, a design methodology is developed, which is based on semi-ideal models for the electronic building blocks. Then a circuit level simulator is used to simulate and evaluate the performance of the control system. Last, the proposed system is implemented with the use of commercial discrete electronic components, all connected on a custom designed printed circuit board (PCB). Simulations of the control system indicate an initialization time less than 160us, and maximum locking voltage error of 1.8%. The obtained dynamic energy consumption is ED=85 fJ/bit/oC for bit rate of 20Gbps. Though the control system is targeted for MRRs, it can be easily expanded to control other PIC devices.