Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling
Following a review of previous work in this area, a presentation is made which illustrates the impact of a naive application of DVS in a system incorporating a time-triggered co-operative (TTC) scheduler. Novel algorithms (TTC-jDVS, TTC-jDVS2) and then introduced which more successfully integrate TT...
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University of Leicester
2007
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| Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.697372 |