| Summary: | Iterative decoders such as Low-Density Parity-Check (LDPC) and turbo decoders have an inherent capability to correct the transmission errors that originate during communication over a hostile wireless channel. This capability has engendered the widespread use of LDPC and turbo decoders in current communications standards. As a result, signficant research efforts have been made in order to conceive efficient Very-Large-Scale Integration (VLSI) implementations of both LDPC and turbo decoders. Typically, these efforts have focused on optimizing only one of the various trade-offs associated with the hardware implementation of iterative decoders, such as the chip area, latency, throughput, energy efficiency or Bit Error Ratio (BER) performance. However, tolerance to timing errors that occur during the iterative decoding processing are typically not considered in these implementations. Owing to this, the BER performance and hardware efficiency of the proposed designs may be severely degraded, if timing errors occur during the iterative decoding process. Against this background, this thesis demonstrates that iterative decoders are capable of exploiting their inherent error correction capability to correct not only transmission errors, but also timing errors caused by overclocking and power supply variations. Moreover,we propose modifications to the iterative decoders designs, which further enhance their inherent tolerance to timing errors. We achieve this by considering the close relationship between the different trade-offs associated with the hardware implementation of iterative decoders, with the aim of achieving Pareto optimality, where none of these trade-offs can be further improved without degrading at least one of the others. Owing to this, our proposed timing-error-tolerant design methodology simultaneously considers the design constraints and parameters that affect not only the BER performance, but also the hardware efficiency of each implementation. We first investigate the benefits of stochastic computing in iterative decoders, by characterizing the inherent timing-error tolerance of Stochastic LDPC Decoders (SLDPCDs) and Stochastic Turbo Decoders (STDs). Moreover, we propose modifications to the SLDPCD and STD in order to further improve their inherent tolerance to timing errors. This is achieved by performing extensive transistor-level and post-layout simulations, in order to develop different timing analyses for determining the causes and effects of timing errors in these stochastic decoders. Following this, we propose a novel Reduced-Latency STD (RLSTD), which improves the latency of the state-of-the-art STD by an order of magnitude, without increasing its chip area or energy consumption. Our experimental results demonstrate that our proposed RLSTD achieves ultra-low-latencies required by next-generation Mission-Critical Machine-Type Communication (MCMTC). We also investigate the inherent tolerance to timing errors of a recently-proposed Fully-Parallel Turbo Decoder (FPTD). Furthermore, we propose a novel Reduced-Critical-Path Fully-Parallel Turbo Decoder (RCP-FPTD) algorithm and the employment of Better-Than-Worst-Case (BTWC) design techniques in FPTD and RCP-FPTD implementations, for the sake of improving their throughput and their tolerance to timing errors caused by overclocking. We demonstrate that the FPTD and RCP-FPTD implementations improve the throughput of the state-of-the-art turbo decoder by an order of magnitude. Finally, despite operating in the presence of timing errors, our proposed Better-Than-Worst-Case Reduced-Critical-Path Fully-Parallel Turbo Decoder (BTWC-RCP-FPTD) achieves throughputs on the order of tens of Gbps, which may be expected to be a requirement in next-generation wireless communication standards.
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