Reliability limitations due to high electric fields of AIGaN/GaN high electron mobility transistors and novel device designs

• Main Author: Moreke, Janina
• Published: University of Bristol 2014
• Subjects: 621.3815
• Online Access: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.680374

This work investigates the impact of electronic trapping on AIGaN/GaN high electron mobility transistor (HEMT) degradation, particularly through the analysis of electric field strength in devices. The demand for ever increasing power capabilities in semiconductor microwave and power switching applications requires an understanding of the physics underlying degradation mechanisms within GaN-based HEMTs in order to be able to develop structures capable to exploit GaN's power capabilities. The investigation of high electric field induced mechanisms therefore contributes to research efforts to increase the power capabilities of state of the art AIGaN/GaN HEMTs. Electrical stressing was performed on AIGaN/GaN HEMTs fabricated on the same epitaxial material to alleviate growth-to-growth variations in the experimental results. Analysis of electrical characterisation before and after electrical stress as well as IV-assisted recovery of different gate geometries showed a tendency towards electronic trap generation depending on the location of the peak electric field. Drift-diffusion simulations confirmed that the peak electric field location was in turn dependent on the gate shape. Device degradation was seen to be most detrimental for peak fields located by the SiNx / AIGaN interface. For better estimation of the electric field strength responsible for degradation through surface trapping, a method using liquid crystal was developed to detect the electric field strength at the surface of the device. This method enabled the verification of drift-diffusion simulations, generally used for electric field strength estimation in AIGaN/GaN HEMTs, by exploiting the ability of molecules in a nematic liquid crystal suspension to respond to an external electric field by aligning according to the field lines. Visualising the set-up through crossed polarisers resulted in images of the drain access region at increasing source-drain bias with dark areas showing molecule alignment. Critical conditions at which maximum molecule alignment in the film was seen, corresponded with simulated results. Due to the direct relationship between the two gimensional ~lectron ~as (2DEG) channel and surface states in AIGaN/GaN devices and the report of a suggested surface passivation straininduced effect on gate leakage currents, AIGaN/GaN HEMTs with complete and partially etched surface passivation layers were investigated with photoluminescence, Raman spectroscopy while pulsed I-V characteristics. Significant additional or reduced strains due to surface passivation, could not be detected in the upper layers of the device excluding a strain-related mechanism, and pulsed I-V characteristics found little surface trapping, but evidence of AIGaN barrier and buffer trapping in these particular devices. Finally, the question of how to create a high power device based on GaN without the need for expensive large scale lateral device designs was addressed by electrically characterising the GaN/GaAs interface, suggesting the use of a GaAs drain substrate for a vertical power GaN device. Following theoretical predictions of a GaN/GaAs conduction band alignment proposing Ohmic interface conduction, experimental results suggest instead the presence of an energy barrier at the interface, the origin of which is not clear. Suggested mechanisms include Nitrogen diffusion resulting in a bandgap variation at the GaN/GaAs interface and the influence of polarisation effects due to a highly strained GaN layer.