| Summary: | The time to market (TTM) for integrated circuits is key to the success for any technology and the products manufactured using it. Today, it is no longer considered economical to continue to debug a technology once it has been released to manufacturing as market share and the development return on investment, are both impacted. This thesis addresses this by proposing a strategy to optimise a given technology. IT uses a combination of Design Of Experiments (DOE), Response Surface Methodology (RSM) and Technology Computer Aided Design (TCAD). The breakdown voltage of an LDMOS technology is optimised, which is well known to be a challenge to model using design experiments and provides a stringent test of the strategy. Covariance models are employed to improve the model fits to the TCAD data with the justification being that the TCAD results have no random error associated with them. This strategy was successfully applied to three technologies where results were comparable to measure data from one silicon iteration and saved at least six months in development, as well as to several other projects within the Analog Process Technology Development group at National Semiconductor, Greenock, Scotland.
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