A formal process for systolic array design using recurrences
A systolic array is essentially a parallel processor which consists of a grid of locally-connected sub-processors which receive, process and pump out data synchronously in such a way that the patterns of data-flow to and from each processor is identical to the flow to and from the other processors....
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University of Edinburgh
1992
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| Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.660797 |