Exploring networks-on-chip for FPGAs
This thesis looks at Network-on-Chip design for FPGAs beyond the trade-offs between hard (silicon) and soft (configurable) designs. FPGAs are capable of extremely flexible statically-routed bit-based wiring, but this flexibility comes at a high area, latency and power cost. In the first part of this...
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University of Cambridge
2009
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| Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.599168 |