Tanlock based loop with improved performance
This thesis is focused on the design, analysis, simulation and implementation of new improved architectures of the Time Delay Digital Tanlock Loop (TDTL) based digital phase-locked loop (DPLL). The proposed architectures overcome some fundamental limitations exhibited by the original TDTL. These lim...
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Manchester Metropolitan University
2012
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| Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582753 |