Application-Specific Number Representation

• Main Author: Fu, Haohuan
• Other Authors: Luk, Wayne ; Mencer, Oskar
• Published: Imperial College London 2009
• Subjects: 502.85
• Online Access: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.506482

Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), enable application-specific number representations. Well-known number formats include fixed-point, floating-point, logarithmic number system (LNS), and residue number system (RNS). Such different number representations lead to different arithmetic designs and error behaviours, thus produc-ing implementations with different performance, accuracy, and cost. To investigate the design options in number representations, the first part of this thesis presentsa platform that enables automated exploration of the number representation design space. Thesecond part of the thesis shows case studies that optimise the designs for area, latency orthroughput from the perspective of number representations. Automated design space exploration in the first part addresses the following two major issues: • Automation requires arithmetic unit generation. This thesis provides optimised arithmetic library generators for logarithmic and residue arithmetic units, which supporta wide range of bit widths and achieve significant improvement over previous designs. • Generation of arithmetic units requires specifying the bit widths for each variable. This thesis describes an automatic bit-width optimisation tool called R-Tool, which combines dynamic and static analysis methods, and supports different number systems (fixed-point, floating-point, and LNS numbers). Putting it all together, the second part explores the effects of application-specific number representation on practical benchmarks, such as radiative Monte Carlo simulation, and seismic imaging computations. Experimental results show that customising the number representations brings benefits to hardware implementations: by selecting a more appropriate number format, we can reduce the area cost by up to 73.5% and improve the throughput by 14.2% to 34.1%; by performing the bit-width optimisation, we can further reduce the area cost by 9.7% to 17.3%. On the performance side, hardware implementations with customised number formats achieve 5 to potentially over 40 times speedup over software implementations.