Design techniques for low power on-chip error correction
As integrated circuit density increases, digital circuits characterized by high operating frequencies and low voltage levels will be increasingly susceptible to faults. Furthermore, it has recently been shown that for many digital signature and identification schemes an attacker can inject faults in...
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University of Bristol
2008
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ndltd-bl.uk-oai-ethos.bl.uk-4924422015-03-20T05:44:31ZDesign techniques for low power on-chip error correctionMathew, Jimson2008As integrated circuit density increases, digital circuits characterized by high operating frequencies and low voltage levels will be increasingly susceptible to faults. Furthermore, it has recently been shown that for many digital signature and identification schemes an attacker can inject faults into the hardware and the resulting incorrect outputs may completely expose their secrets. On-chip error masking techniques such as error correction could be one of the options to mitigate the above problems. To this end, this thesis presents a framework of techniques to design error circuits.621.3815University of Bristolhttp://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.492442Electronic Thesis or Dissertation |
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621.3815 |
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621.3815 Mathew, Jimson Design techniques for low power on-chip error correction |
| description |
As integrated circuit density increases, digital circuits characterized by high operating frequencies and low voltage levels will be increasingly susceptible to faults. Furthermore, it has recently been shown that for many digital signature and identification schemes an attacker can inject faults into the hardware and the resulting incorrect outputs may completely expose their secrets. On-chip error masking techniques such as error correction could be one of the options to mitigate the above problems. To this end, this thesis presents a framework of techniques to design error circuits. |
| author |
Mathew, Jimson |
| author_facet |
Mathew, Jimson |
| author_sort |
Mathew, Jimson |
| title |
Design techniques for low power on-chip error correction |
| title_short |
Design techniques for low power on-chip error correction |
| title_full |
Design techniques for low power on-chip error correction |
| title_fullStr |
Design techniques for low power on-chip error correction |
| title_full_unstemmed |
Design techniques for low power on-chip error correction |
| title_sort |
design techniques for low power on-chip error correction |
| publisher |
University of Bristol |
| publishDate |
2008 |
| url |
http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.492442 |
| work_keys_str_mv |
AT mathewjimson designtechniquesforlowpoweronchiperrorcorrection |
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