Satellite on-board encryption

• Main Author: Banu, Pokhali Sayeda Roohi
• Published: University of Surrey 2007
• Subjects: 384.51
• Online Access: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.442631

In the light of latest intrusions into satellite data the demand to protect the sensitive and valuable data transmitted from satellites to ground has increased and hence the need to use encryption on-board. The Advanced Encryption Standard (AES), which is a very popular choice in terrestrial communications, is slowly emerging as the preferred option in the aerospace industry including satellites. Computing systems on-board satellites have limited power and computational resources as in terrestrial embedded systems. With these constraints in mind various implementations of the AES algorithm using different optimization techniques have been carried out on FPGAs and the implementations have been evaluated in terms of power, throughput and device area. Satellites operate in a harsh radiation environment and consequently any electronic system used on board, including the encryption processor, is susceptible to radiationinduced faults. Hence, in addition to consuming limited resources, the encryption processor should be immune to radiation induced faults to avoid faulty data transmission to ground station. Most of the faults that occur in satellite on-board electronic devices are radiation induced bit flips called single event upsets (SEUs). A detailed novel analysis of the effect of faults on imaging and telemetry data during onboard encryption is carried out. Also the impact of faults in the data which occur during transmission to the ground station due to noisy channels is discussed and compared. In order to avoid data corruption due to SEUs a novel fault-tolerant model of the AES is presented, which is based on the Hamming error correction code. Implementation of the proposed model is carried out on FPGAs and measurements of the power and throughput overhead are presented.