Multiple restricted multiplication for optimized FPGA-based arithmetic

Multiple restricted multiplication for optimized FPGA-based arithmetic

Bibliographic Details
Main Author: Sidahao, Nalin
Published: Imperial College London 2005
Subjects:
621.395
Online Access:http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.420639
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spelling ndltd-bl.uk-oai-ethos.bl.uk-4206392015-03-19T10:15:54ZMultiple restricted multiplication for optimized FPGA-based arithmeticSidahao, Nalin2005621.395Imperial College Londonhttp://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.420639Electronic Thesis or Dissertation
collection NDLTD
sources NDLTD
topic 621.395
spellingShingle 621.395
Sidahao, Nalin
Multiple restricted multiplication for optimized FPGA-based arithmetic
author Sidahao, Nalin
author_facet Sidahao, Nalin
author_sort Sidahao, Nalin
title Multiple restricted multiplication for optimized FPGA-based arithmetic
title_short Multiple restricted multiplication for optimized FPGA-based arithmetic
title_full Multiple restricted multiplication for optimized FPGA-based arithmetic
title_fullStr Multiple restricted multiplication for optimized FPGA-based arithmetic
title_full_unstemmed Multiple restricted multiplication for optimized FPGA-based arithmetic
title_sort multiple restricted multiplication for optimized fpga-based arithmetic
publisher Imperial College London
publishDate 2005
url http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.420639
work_keys_str_mv AT sidahaonalin multiplerestrictedmultiplicationforoptimizedfpgabasedarithmetic
_version_ 1716774063763881984

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