A logic synthesis approach to silicon compilation

Bibliographic Details
Main Author:	Padua, C. I. P. S.
Published:	University of Southampton 1988
Subjects:	621.3192 VSLI circuit design
Online Access:	http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.381234

id	ndltd-bl.uk-oai-ethos.bl.uk-381234
record_format	oai_dc
spelling	ndltd-bl.uk-oai-ethos.bl.uk-3812342015-03-19T08:46:52ZA logic synthesis approach to silicon compilationPadua, C. I. P. S.1988621.3192VSLI circuit designUniversity of Southamptonhttp://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.381234Electronic Thesis or Dissertation
collection	NDLTD
sources	NDLTD
topic	621.3192 VSLI circuit design
spellingShingle	621.3192 VSLI circuit design Padua, C. I. P. S. A logic synthesis approach to silicon compilation
author	Padua, C. I. P. S.
author_facet	Padua, C. I. P. S.
author_sort	Padua, C. I. P. S.
title	A logic synthesis approach to silicon compilation
title_short	A logic synthesis approach to silicon compilation
title_full	A logic synthesis approach to silicon compilation
title_fullStr	A logic synthesis approach to silicon compilation
title_full_unstemmed	A logic synthesis approach to silicon compilation
title_sort	logic synthesis approach to silicon compilation
publisher	University of Southampton
publishDate	1988
url	http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.381234
work_keys_str_mv	AT paduacips alogicsynthesisapproachtosiliconcompilation AT paduacips logicsynthesisapproachtosiliconcompilation
_version_	1716767000713232384

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