High level behavioural modelling of boundary scan architecture
This project involves the development of a software tool which enables the integration of the IEEE 1149.1/JTAG Boundary Scan Test Architecture automatically into an ASIC (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 10...
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Bournemouth University
1993
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| Online Access: | http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.333480 |