Optimising fault modelling and test development for VLSI analogue circuits

Bibliographic Details
Main Author:	Besnard, SteÌphane Claude Louis
Published:	University of Huddersfield 2001
Subjects:	621.3950287 Electronic testing
Online Access:	http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.288503

id	ndltd-bl.uk-oai-ethos.bl.uk-288503
record_format	oai_dc
spelling	ndltd-bl.uk-oai-ethos.bl.uk-2885032015-03-19T06:40:18ZOptimising fault modelling and test development for VLSI analogue circuitsBesnard, SteÌphane Claude Louis2001621.3950287Electronic testingUniversity of Huddersfieldhttp://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.288503Electronic Thesis or Dissertation
collection	NDLTD
sources	NDLTD
topic	621.3950287 Electronic testing
spellingShingle	621.3950287 Electronic testing Besnard, SteÌphane Claude Louis Optimising fault modelling and test development for VLSI analogue circuits
author	Besnard, SteÌphane Claude Louis
author_facet	Besnard, SteÌphane Claude Louis
author_sort	Besnard, SteÌphane Claude Louis
title	Optimising fault modelling and test development for VLSI analogue circuits
title_short	Optimising fault modelling and test development for VLSI analogue circuits
title_full	Optimising fault modelling and test development for VLSI analogue circuits
title_fullStr	Optimising fault modelling and test development for VLSI analogue circuits
title_full_unstemmed	Optimising fault modelling and test development for VLSI analogue circuits
title_sort	optimising fault modelling and test development for vlsi analogue circuits
publisher	University of Huddersfield
publishDate	2001
url	http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.288503
work_keys_str_mv	AT besnardsteiphaneclaudelouis optimisingfaultmodellingandtestdevelopmentforvlsianaloguecircuits
_version_	1716750976625410048

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