Partial dynamic reconfiguration of FPGAs for systolic circuits

Bibliographic Details
Main Author:	Cadenas Medina, Oswaldo
Published:	University of Reading 2002
Subjects:	621 Parallel algorithms
Online Access:	http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.270913

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record_format	oai_dc
spelling	ndltd-bl.uk-oai-ethos.bl.uk-2709132015-03-20T03:53:25ZPartial dynamic reconfiguration of FPGAs for systolic circuitsCadenas Medina, Oswaldo2002621Parallel algorithmsUniversity of Readinghttp://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.270913http://centaur.reading.ac.uk/18884/Electronic Thesis or Dissertation
collection	NDLTD
sources	NDLTD
topic	621 Parallel algorithms
spellingShingle	621 Parallel algorithms Cadenas Medina, Oswaldo Partial dynamic reconfiguration of FPGAs for systolic circuits
author	Cadenas Medina, Oswaldo
author_facet	Cadenas Medina, Oswaldo
author_sort	Cadenas Medina, Oswaldo
title	Partial dynamic reconfiguration of FPGAs for systolic circuits
title_short	Partial dynamic reconfiguration of FPGAs for systolic circuits
title_full	Partial dynamic reconfiguration of FPGAs for systolic circuits
title_fullStr	Partial dynamic reconfiguration of FPGAs for systolic circuits
title_full_unstemmed	Partial dynamic reconfiguration of FPGAs for systolic circuits
title_sort	partial dynamic reconfiguration of fpgas for systolic circuits
publisher	University of Reading
publishDate	2002
url	http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.270913
work_keys_str_mv	AT cadenasmedinaoswaldo partialdynamicreconfigurationoffpgasforsystoliccircuits
_version_	1716782674651119616

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