6T-SRAM 1Mb Design with Test Structures and Post Silicon Validation
abstract: Static random-access memories (SRAM) are integral part of design systems as caches and data memories that and occupy one-third of design space. The work presents an embedded low power SRAM on a triple well process that allows body-biasing control. In addition to the normal mode operation,...
Other Authors: | Dosi, Ankita (Author) |
---|---|
Format: | Dissertation |
Language: | English |
Published: |
2017
|
Subjects: | |
Online Access: | http://hdl.handle.net/2286/R.I.45000 |
Similar Items
-
Post-silicon Validation of Radiation Hardened Microprocessor and SRAM arrays
Published: (2017) -
Scalable SRAM design
by: Wuu, John J. (John Jung-Sheun)
Published: (2008) -
Design and characterization of 6T SRAM
by: Lin, Yi-Wei, et al.
Published: (2010) -
40nm 1.0Mb 6T Pipeline SRAM with Step-Up Word- Line and Adaptive-Data-Aware Write-Assist Design
by: Chang, chi-Shin, et al.
Published: (2011) -
Post-silicon Validation of Radiation Hardened Microprocessor, Embedded Flash and Test Structures
Published: (2016)