A Study On The Effects Of Ground Via Fences, Embedded Patterned Layer, And Metal Surface Roughness On Conductor Backed Coplanar Waveguide
Electrical engineers have responded to the increasing demand for circuit speed and functionality by reducing transistor feature size and increasing on-chip transistor density. Consequently, interconnect density, both on-chip and the system level is also increasing. Increasing circuit speed translate...
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| Language: | en_US |
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The University of Arizona.
2015
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| Online Access: | http://hdl.handle.net/10150/593602 |