Evaluation of a LSI fault detection program using a four bit micro-computer processor circuit

Evaluation of a LSI fault detection program using a four bit micro-computer processor circuit

Bibliographic Details
Main Author:	Ng, Wai Wing, 1949-
Language:	en_US
Published:	The University of Arizona. 1974
Subjects:	SCIRTSS (Computer program) Digital integrated circuits > Testing. Logic circuits > Testing. Electric fault location > Data processing.
Online Access:	http://hdl.handle.net/10150/554657

Similar Items

FAULT-TEST GENERATION FOR SEQUENTIAL CIRCUITS DESCRIBED IN AHPL
by: Carter, Ernest Aubert, 1942-
Published: (1973)

Evaluation of SCIRTSS performance on sequential circuits biased against random sequences
by: Van Helsland, Marshall Camiel, 1943-
Published: (1974)

Sensitivity of SCIRTSS to weighted heuristic functions
by: Callaway, Thomas Morriss, 1947-
Published: (1975)

SEARCH DIRECTING HEURISTICS FOR THE SEQUENTIAL CIRCUIT TEST SEARCH SYSTEM (SCIRTSS)
by: Huey, Ben Milton, 1945-
Published: (1975)

A programmed test sequence generation to detect and distinguish failures in a combinational circuit
by: Huang, George Huang-Liang, 1938-
Published: (1973)

An interactive program for determination of fault detecting sequences
by: Lin, Liang-Tsai, 1944-
Published: (1970)

Fault isolation and diagnosis techniques for mixed-signal circuits
by: Cherubal, Sasikumar
Published: (2007)

AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS
by: Belt, John Edward, 1933-
Published: (1973)

Distribution fault location using short-circuit fault current profile approach
by: Das, Swagata
Published: (2012)

EXTENSIONS OF AHPL AND OPTIMIZATION OF THE AHPL COMPILER FOR MSI/LSI DESIGN
by: Swanson, Robert Earl, 1944-
Published: (1978)

New digital testing for parametric fault detection in analog circuits using classified frequency-bands and efficient test-point selection
by: Bassam A. Abo-elftooh, et al.
Published: (2021-06-01)

COMPARISON OF SCIRTSS EFFICIENCY WITH D-ALGORITHM APPLICATION TO ITERATIVE NETWORKS (TEST).
by: Chen, Daven, 1959-
Published: (1986)

Conditional stuck-at fault model for PLA test generation
by: Cornelia, Olivian E.
Published: (1987)

Multiple Soft Fault Diagnosis of Bjt Circuits
by: Tadeusiewicz Michał, et al.
Published: (2014-12-01)

Test support processor for enhanced testability of high performance integrated circuits
by: Zhou, Qing
Published: (2006)

Defect site prediction based upon statistical analysis of fault signatures
by: Trinka, Michael Robert
Published: (2004)

Test generation for fault isolation in analog and mixed-mode circuits
by: Chakrabarti, Sudip
Published: (2007)

Automated diagnosis of path delay faults in digital integrated circuits
by: Pant, Pankaj
Published: (2007)

Concurrent fault simulation for mixed-signal circuits
by: Hou, Junwei
Published: (2007)

Detecting bridging faults in CMOS circuits
by: Evans, Richard J.
Published: (1991)

Synchronous fault simulation by surrogate with exceptions.
by: Wang, Xiaolin.
Published: (1989)

DESIGN AND TEST GENERATION FOR CLOCK SKEW FAULTS OF CLOCK-DELAYED DOMINO LOGIC CIRCUITS
by: MAO, WUJIN
Published: (2007)

Case based reasoning as an extension of fault dictionary methods for linear electronic analog circuits diagnosis
by: Pous i Sabadí, Carles
Published: (2004)

Macrosimulation of LSI circuits for timing and waveform data
by: Fyson, C. J. R.
Published: (1986)

Fault Location in Double Circuit Medium Power Distribution Networks Using an Impedance-Based Method
by: Rahman Dashti, et al.
Published: (2018-06-01)

Fault Modeling of Graphene Nanoribbon FET Logic Circuits
by: D. Gil-Tomàs, et al.
Published: (2019-07-01)

Sequential circuits fault simulation using fan out stem based techniques.
by: Abuelyaman, Eltayeb Salih.
Published: (1988)

An intelligence driven test system for detection of stuck-open faults in CMOS sequential circuits
by: Sagahyroon, Assim Abdelrahman
Published: (1989)

COMPUTER ANALYSIS OF ACTIVE DEVICES FOR INTEGRATED THERMIONIC CIRCUITS
by: Feugate, Robert J., 1946-
Published: (1974)

A Novel Traveling-Wave-Based Method Improved by Unsupervised Learning for Fault Location of Power Cables via Sheath Current Monitoring
by: Mingzhen Li, et al.
Published: (2019-05-01)

Fault simulation for stuck-open faults in CMOS combinational circuits
by: Su, Lang
Published: (1993)

A Fault Location Method Using Direct Convolution: Electromagnetic Time Reversal or Not Reversal
by: Wang, G., et al.
Published: (2022)

An efficient single-latch scan-design scheme/
by: Panda, Uma R.
Published: (1985)

Test et LSI
by: Courtois, Beranrd
Published: (1981)

Experimental Study Of Fault Cones And Fault Aliasing
by: Bilagi, Vedanth
Published: (2012)

Current mode analog and digital circuit design
by: Liang, Guojin
Published: (2013)

Enhanced Fault Current-Limiting Circuit Design for a DC Fault in a Modular Multilevel Converter-Based High-Voltage Direct Current System
by: Kaipei Liu, et al.
Published: (2019-04-01)

An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University
by: Lee, Hoon-Kyeu
Published: (1986)

Non-contact fault location and identification method for same-tower multi-circuit transmission lines
by: Tao Yin, et al.
Published: (2021-04-01)

Fault simulation and test pattern generation for synchronous and asynchronous sequential circuits
by: Lee, Hyung Ki
Published: (2014)