Design Techniques for Timing Circuits in Wireline and Wireless Communication Systems
Clock and data recovery (CDR) circuit and frequency synthesizer are two essential timing circuits in wireline and wireless communication systems, respectively. With multigigabits/s high speed links and emerging 4G wireless system widely used in communication backbone infrastructures and consumer ele...
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| Language: | en_US |
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The University of Arizona.
2014
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| Online Access: | http://hdl.handle.net/10150/344107 |