The effect of die attach voiding on the thermal resistance of integrated circuit package
The effect of die attach voiding on the thermal resistance of a hybrid integrated circuit package has been investigated. Voids with precisely controlled geometry, morphology, distribution, and different volume percentages are fabricated in the backside of the silicon chips by modern micro-photolitho...
| Main Author: | |
|---|---|
| Other Authors: | |
| Language: | en_US |
| Published: |
The University of Arizona.
1987
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10150/276568 |
| id |
ndltd-arizona.edu-oai-arizona.openrepository.com-10150-276568 |
|---|---|
| record_format |
oai_dc |
| spelling |
ndltd-arizona.edu-oai-arizona.openrepository.com-10150-2765682015-10-23T05:01:56Z The effect of die attach voiding on the thermal resistance of integrated circuit package Chang, Li-hsin, 1946- Johnson, Barry C. Integrated circuits -- Design. Heat -- Transmission. The effect of die attach voiding on the thermal resistance of a hybrid integrated circuit package has been investigated. Voids with precisely controlled geometry, morphology, distribution, and different volume percentages are fabricated in the backside of the silicon chips by modern micro-photolithographic techniques. A large thin film resistor over the entire chip surface area served as a uniform heat generating source. A TO-3 steel package with beryllia substrate is used for chip packaging. Correlation of thermal resistance to power dissipation in the range studied is presented and discussed. The dependence of thermal resistance on void characteristics and total void area are demonstrated through infrared mapping of chip surface temperature; and the correlations are qualitatively analyzed. A brief discussion on die bond void reduction is also given. 1987 text Thesis-Reproduction (electronic) http://hdl.handle.net/10150/276568 19534408 1332412 .b16796706 en_US Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. The University of Arizona. |
| collection |
NDLTD |
| language |
en_US |
| sources |
NDLTD |
| topic |
Integrated circuits -- Design. Heat -- Transmission. |
| spellingShingle |
Integrated circuits -- Design. Heat -- Transmission. Chang, Li-hsin, 1946- The effect of die attach voiding on the thermal resistance of integrated circuit package |
| description |
The effect of die attach voiding on the thermal resistance of a hybrid integrated circuit package has been investigated. Voids with precisely controlled geometry, morphology, distribution, and different volume percentages are fabricated in the backside of the silicon chips by modern micro-photolithographic techniques. A large thin film resistor over the entire chip surface area served as a uniform heat generating source. A TO-3 steel package with beryllia substrate is used for chip packaging. Correlation of thermal resistance to power dissipation in the range studied is presented and discussed. The dependence of thermal resistance on void characteristics and total void area are demonstrated through infrared mapping of chip surface temperature; and the correlations are qualitatively analyzed. A brief discussion on die bond void reduction is also given. |
| author2 |
Johnson, Barry C. |
| author_facet |
Johnson, Barry C. Chang, Li-hsin, 1946- |
| author |
Chang, Li-hsin, 1946- |
| author_sort |
Chang, Li-hsin, 1946- |
| title |
The effect of die attach voiding on the thermal resistance of integrated circuit package |
| title_short |
The effect of die attach voiding on the thermal resistance of integrated circuit package |
| title_full |
The effect of die attach voiding on the thermal resistance of integrated circuit package |
| title_fullStr |
The effect of die attach voiding on the thermal resistance of integrated circuit package |
| title_full_unstemmed |
The effect of die attach voiding on the thermal resistance of integrated circuit package |
| title_sort |
effect of die attach voiding on the thermal resistance of integrated circuit package |
| publisher |
The University of Arizona. |
| publishDate |
1987 |
| url |
http://hdl.handle.net/10150/276568 |
| work_keys_str_mv |
AT changlihsin1946 theeffectofdieattachvoidingonthethermalresistanceofintegratedcircuitpackage AT changlihsin1946 effectofdieattachvoidingonthethermalresistanceofintegratedcircuitpackage |
| _version_ |
1718102315067506688 |