Power Analysis of Sub-threshold Logics for Security Applications
Requirements of ultra-low power for many portable devices have drawn increased attention to digital sub-threshold logic design. Major reductions in power consumption and frequency of operation degradation due to the exponential decrease of the drain current in the sub-threshold region has made this...
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| Language: | en |
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2012
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| Online Access: | http://hdl.handle.net/10012/7019 |