Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA
This thesis presents a new architecture for the reliable implementation of the symmetric-key algorithm Advanced Encryption Standard (AES) in Field Programmable Gate Arrays (FPGAs). Since FPGAs are prone to soft errors caused by radiation, and AES is highly sensitive to errors, reliable architectures...
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| Language: | en |
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2011
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| Online Access: | http://hdl.handle.net/10012/5792 |