Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation
With significant research effort being directed towards designing lightweight cryptographic primitives, logical metrics such as gate count are extensively used in estimating their hardware quality. Specialized logic minimization tools have been built to make use of gate count as the primary optimiza...
Main Author: | Raghuraman, Shashank |
---|---|
Other Authors: | Electrical and Computer Engineering |
Format: | Others |
Published: |
Virginia Tech
2019
|
Subjects: | |
Online Access: | http://hdl.handle.net/10919/91462 |
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