Integration of VHDL simulation and test verification into a Process Model Graph design environment
This thesis discusses the ability to maintain a consistent design, simulation, and test verification environment by use of the Process Model Graph (PMG) throughout the development process. This ability extends the functionality of the PMG to include the visualization of simulation results and the...
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| Format: | Others |
| Language: | en |
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/46017 http://scholar.lib.vt.edu/theses/available/etd-11242009-020247/ |