The E-algorithm: an automatic test generation algorithm for hardware description languages

• Main Author: Norrod, Forrest Eugene
• Other Authors: Electrical Engineering
• Format: Others
• Published: Virginia Tech 2014
• Subjects: LD5655.V855 1988.N677; Algorithms; Integrated circuits > Very large scale integration
• Online Access: http://hdl.handle.net/10919/43260; http://scholar.lib.vt.edu/theses/available/etd-06122010-020406/

Traditional test generation techniques for digital circuits have been rendered inadequate by the increasing levels of integration achieved by VLSI technology. This thesis presents a test generation algorithm, the E-algorithm, that generates tests for circuits described using the VHDL Hardware Description Language. A fault model has been developed that addresses data path faults, faults in control structures, and faults in functional operators. The E-algorithm is able to generate tests for all modeled fault types, and handles a wide variety of circuit types, including sequential circuits. The algorithm has been implemented; preliminary results are given. === Master of Science