Development of VHDL behavioral models with back annotated timing

Development of VHDL behavioral models with back annotated timing

This thesis describes the development of BACKANN, a tool for the back annotation of timing delays into VHDL models. BACKANN uses the Process Model Graph and the VHDL behavioral model generated by the Modeler's Assistant as the base for backannotation. BACKANN determines the delay values that ar...

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Bibliographic Details
Main Author: Narayanaswamy, Sathyanarayanan
Other Authors: Electrical Engineering
Format: Others
Language:en
Published: Virginia Tech 2014
Subjects:
LD5655.V855 1994.N373
Integrated circuits > Very large scale integration > Computer simulation
VHDL (Computer hardware description language)
Online Access:http://hdl.handle.net/10919/43158
http://scholar.lib.vt.edu/theses/available/etd-06112009-063442/
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spelling ndltd-VTETD-oai-vtechworks.lib.vt.edu-10919-431582021-05-26T05:48:37Z Development of VHDL behavioral models with back annotated timing Narayanaswamy, Sathyanarayanan Electrical Engineering LD5655.V855 1994.N373 Integrated circuits -- Very large scale integration -- Computer simulation VHDL (Computer hardware description language) This thesis describes the development of BACKANN, a tool for the back annotation of timing delays into VHDL models. BACKANN uses the Process Model Graph and the VHDL behavioral model generated by the Modeler's Assistant as the base for backannotation. BACKANN determines the delay values that are required for the signal assignments in the behavioral model. It generates a gate-level design of the model using the Synopsys Design Compiler. It extracts the values for the delays required from the gate-level design. It then back-annotates these values into the VHDL behavioral model. BACKANN is thus a design automation tool that helps the development of VHDL behavioral models with realistic timing and thus quickens the design cycle. Master of Science 2014-03-14T21:37:57Z 2014-03-14T21:37:57Z 1994 2009-06-11 2009-06-11 2009-06-11 Thesis Text etd-06112009-063442 http://hdl.handle.net/10919/43158 http://scholar.lib.vt.edu/theses/available/etd-06112009-063442/ en OCLC# 30815762 LD5655.V855_1994.N373.pdf In Copyright http://rightsstatements.org/vocab/InC/1.0/ x, 112 leaves BTD application/pdf application/pdf Virginia Tech
collection NDLTD
language en
format Others
sources NDLTD
topic LD5655.V855 1994.N373
Integrated circuits -- Very large scale integration -- Computer simulation
VHDL (Computer hardware description language)
spellingShingle LD5655.V855 1994.N373
Integrated circuits -- Very large scale integration -- Computer simulation
VHDL (Computer hardware description language)
Narayanaswamy, Sathyanarayanan
Development of VHDL behavioral models with back annotated timing
description This thesis describes the development of BACKANN, a tool for the back annotation of timing delays into VHDL models. BACKANN uses the Process Model Graph and the VHDL behavioral model generated by the Modeler's Assistant as the base for backannotation. BACKANN determines the delay values that are required for the signal assignments in the behavioral model. It generates a gate-level design of the model using the Synopsys Design Compiler. It extracts the values for the delays required from the gate-level design. It then back-annotates these values into the VHDL behavioral model. BACKANN is thus a design automation tool that helps the development of VHDL behavioral models with realistic timing and thus quickens the design cycle. === Master of Science
author2 Electrical Engineering
author_facet Electrical Engineering
Narayanaswamy, Sathyanarayanan
author Narayanaswamy, Sathyanarayanan
author_sort Narayanaswamy, Sathyanarayanan
title Development of VHDL behavioral models with back annotated timing
title_short Development of VHDL behavioral models with back annotated timing
title_full Development of VHDL behavioral models with back annotated timing
title_fullStr Development of VHDL behavioral models with back annotated timing
title_full_unstemmed Development of VHDL behavioral models with back annotated timing
title_sort development of vhdl behavioral models with back annotated timing
publisher Virginia Tech
publishDate 2014
url http://hdl.handle.net/10919/43158
http://scholar.lib.vt.edu/theses/available/etd-06112009-063442/
work_keys_str_mv AT narayanaswamysathyanarayanan developmentofvhdlbehavioralmodelswithbackannotatedtiming
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