Probability of latching single event upset errors in VLSI circuits
The ability of radiation to cause transient faults in space borne as well as ground based computers is well known. with the density of VLSI circuits increasing every year, the probability of an upset by radiation is becoming more likely. However, research in this area has matured over the last decad...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en |
| Published: |
Virginia Tech
2014
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10919/41980 http://scholar.lib.vt.edu/theses/available/etd-04082009-040435/ |
| Summary: | The ability of radiation to cause transient faults in space
borne as well as ground based computers is well known. with
the density of VLSI circuits increasing every year, the
probability of an upset by radiation is becoming more likely.
However, research in this area has matured over the last
decade, and the mechanisms which cause such faults are better
understood. This understanding enables us to propose ideas to
eliminate or lessen the effects of radiation on VLSI circuits.
<p>Most of the research to date has concentrated on the effect of
transient faults on flip-flops rather than combinational
logic. This is due to several reasons. First, transient
faults, also known as Single Event Upsets (SEU), were first
observed in memory circuits located on board satellites.
Second, an SEU can leave a lasting effect on a circuit if it
occurs in a flip-flop, and third, SEUs can cause the output of
a flip-flop to change state more easily if it occurs directly
in the flip-flop rather than in the combinational logic.
<p>In combinational logic, the node struck by the radiation is
completely disjoint from the flip-flops output node. This in
effect causes the SEU to satisfy more criteria in order to
change the flip-flops output state. The criteria that the SEU
must satisfy tend to be complex, and this complexity has
caused many researchers to believe that SEUs that occur in
combinational logic cause negligible errors in the state of
flip-flops.
<p>Thus, in this thesis, the criteria for latching a SEU are
discussed, and original methods are presented that can be used
to determine the probability of an SEU occurring at any node
in a circuit will cause a change in the output state of a
flip-flop. The methods are then incorporated into a program,
named SUPER II, that is able to evaluate the circuit to
determine the nodes with the highest probability of having a
SEU error latched. The results from the program show that
SEUs that occur in combinational logic can have a significant
probability of becoming latched. === Master of Science |
|---|