Efficient Binary Field Multiplication on a VLIW DSP

• Main Author: Tergino, Christian Sean
• Other Authors: Electrical and Computer Engineering
• Format: Others
• Published: Virginia Tech 2014
• Subjects: Very Long Instruction Word; Modular Multiplication; C64x+; Digital Signal Processor; Multiplication; Binary Field; Galois Field; GF; Heterogeneous Multiprocessors
• Online Access: http://hdl.handle.net/10919/33693; http://scholar.lib.vt.edu/theses/available/etd-06222009-150103/

Modern public-key cryptography relies extensively on modular multiplication with long operands. We investigate the opportunities to optimize this operation in a heterogeneous multiprocessing platform such as TI OMAP3530. By migrating the long operand modular multiplication from a general-purpose ARM Cortex A8 to a specialized C64x+ VLIW DSP, we are able to exploit the XOR-Multiply instruction and the inherent parallelism of the DSP. The proposed multiplication utilizes Multi-Precision Binary Polynomial Multiplication with Unbalanced Exponent Modular Reduction. The resulting DSP implementation performs a GF(2^233) multiplication in less than 1.31us, which is over a seven times speed up when compared with the ARM implementation on the same chip. We present several strategies for different field sizes and field polynomials, and show that a 360MHz DSP easily outperforms the 500MHz ARM. === Master of Science