Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers
Continuous advances in VLSI technology have led to more complex digital designs and shrinking transistor sizes. Due to these developments, design verification and manufacturing test have gained more importance and 70 % of the design expenditure in on validation processes. Electronic Design Automatio...
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/31153 http://scholar.lib.vt.edu/theses/available/etd-02062012-153606/ |