A Test Planning System for Functional Validation of VHDL DSP Models
Validating DSP circuits modeled in VHDL involves generating test data, creating VHDL test benches, and simulating the test benches including models under test (MUTs). This is a laborious and time-consuming process. Therefore, it is desirable to develop a high level approach to automating and plannin...
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/30305 http://scholar.lib.vt.edu/theses/available/etd-1598-132027/ |