Self-Modifying Circuitry for Efficient, Defect-Tolerant Handling of Trillion-element Reconfigurable Devices

As VLSI circuits continue to have more and more transistors over time, the question of not only how to use, but how to manage the complexity of so many transistors becomes increasingly important. Four hypothesis are given for the design of a system that scales-up as transistors continue to shrink. A...

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Bibliographic Details
Main Author: Macias, Nicholas J.
Other Authors: Electrical and Computer Engineering
Format: Others
Published: Virginia Tech 2014
Subjects:
Online Access:http://hdl.handle.net/10919/27665
http://scholar.lib.vt.edu/theses/available/etd-05112011-173844/
id ndltd-VTETD-oai-vtechworks.lib.vt.edu-10919-27665
record_format oai_dc
spelling ndltd-VTETD-oai-vtechworks.lib.vt.edu-10919-276652020-10-17T06:35:20Z Self-Modifying Circuitry for Efficient, Defect-Tolerant Handling of Trillion-element Reconfigurable Devices Macias, Nicholas J. Electrical and Computer Engineering Athanas, Peter M. Abbott, A. Lynn Jones, Alex K. Martin, Thomas L. Patterson, Cameron D. non-dualism fault handling parallelism FPGA self-modifying self-configurable reconfigurable Avogadro machine As VLSI circuits continue to have more and more transistors over time, the question of not only how to use, but how to manage the complexity of so many transistors becomes increasingly important. Four hypothesis are given for the design of a system that scales-up as transistors continue to shrink. An architecture is presented that satisfies these hypothesis, and the motivation behind the hypothesis is further explained. The use of this architecture's unique features to implement an efficient, defect-tolerant parallel bootstrap system is discussed. A detailed methodology for implementing this system in vivo is described. A sample problem--simulation of heat flow--is presented, and its solution using the proposed architecture is described in detail. A comparison is made between the proposed architecture and a set of contemporary architectures, and the former is shown to have desirable performance in a number of areas. Conclusion are given, and plans for future work are presented. Ph. D. 2014-03-14T20:11:54Z 2014-03-14T20:11:54Z 2011-04-29 2011-05-11 2011-05-31 2011-05-31 Dissertation etd-05112011-173844 http://hdl.handle.net/10919/27665 http://scholar.lib.vt.edu/theses/available/etd-05112011-173844/ Macias_NJ_D_2011.pdf In Copyright http://rightsstatements.org/vocab/InC/1.0/ application/pdf Virginia Tech
collection NDLTD
format Others
sources NDLTD
topic non-dualism
fault handling
parallelism
FPGA
self-modifying
self-configurable
reconfigurable
Avogadro machine
spellingShingle non-dualism
fault handling
parallelism
FPGA
self-modifying
self-configurable
reconfigurable
Avogadro machine
Macias, Nicholas J.
Self-Modifying Circuitry for Efficient, Defect-Tolerant Handling of Trillion-element Reconfigurable Devices
description As VLSI circuits continue to have more and more transistors over time, the question of not only how to use, but how to manage the complexity of so many transistors becomes increasingly important. Four hypothesis are given for the design of a system that scales-up as transistors continue to shrink. An architecture is presented that satisfies these hypothesis, and the motivation behind the hypothesis is further explained. The use of this architecture's unique features to implement an efficient, defect-tolerant parallel bootstrap system is discussed. A detailed methodology for implementing this system in vivo is described. A sample problem--simulation of heat flow--is presented, and its solution using the proposed architecture is described in detail. A comparison is made between the proposed architecture and a set of contemporary architectures, and the former is shown to have desirable performance in a number of areas. Conclusion are given, and plans for future work are presented. === Ph. D.
author2 Electrical and Computer Engineering
author_facet Electrical and Computer Engineering
Macias, Nicholas J.
author Macias, Nicholas J.
author_sort Macias, Nicholas J.
title Self-Modifying Circuitry for Efficient, Defect-Tolerant Handling of Trillion-element Reconfigurable Devices
title_short Self-Modifying Circuitry for Efficient, Defect-Tolerant Handling of Trillion-element Reconfigurable Devices
title_full Self-Modifying Circuitry for Efficient, Defect-Tolerant Handling of Trillion-element Reconfigurable Devices
title_fullStr Self-Modifying Circuitry for Efficient, Defect-Tolerant Handling of Trillion-element Reconfigurable Devices
title_full_unstemmed Self-Modifying Circuitry for Efficient, Defect-Tolerant Handling of Trillion-element Reconfigurable Devices
title_sort self-modifying circuitry for efficient, defect-tolerant handling of trillion-element reconfigurable devices
publisher Virginia Tech
publishDate 2014
url http://hdl.handle.net/10919/27665
http://scholar.lib.vt.edu/theses/available/etd-05112011-173844/
work_keys_str_mv AT maciasnicholasj selfmodifyingcircuitryforefficientdefecttoleranthandlingoftrillionelementreconfigurabledevices
_version_ 1719352733615521792