| Summary: | Modern ICs need to be designed with proper designer-controllable factors to meet power, speed and single-event (SE) performance requirements in different applications. Commercial fabrication houses have successfully transitioned to FinFET structure for advanced semiconductor processes. For FinFET technologies, since the physical structure changes significantly compared to planar technologies, the underlying charge collection mechanism at a circuit node evolves that most single-event effects need to be reevaluated for FinFET technologies. This work characterizes SE performance for flip-flop (FF) designs in a commercial 14/16-nm bulk FinFET technology from a designerâs perspective. For the first time, effects of designer-controlled parameters related to fabrication process, such as threshold voltage, dual- and triple-well processes, on SE performance and power consumption have been investigated in FinFET technologies. Theoretic analysis, simulation and experimental results are used to understand the effects of threshold voltage and well structure on SE upset responses. By comparing with former planar technologies, this work provides designers with better understanding of how SE mechanism evolves from planar to FinFET technologies, better idea of overall SE performance for FF designs and provide design guidelines for choosing proper designer-controlled parameters for specific applications in FinFET technologies.
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