Thermo-mechanical stress analysis and interfacial reliabiity for through-silicon vias in three-dimensional interconnect structures

Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future...

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Bibliographic Details
Main Author: Ryu, Suk-Kyu
Format: Others
Language:English
Published: 2012
Subjects:
Online Access:http://hdl.handle.net/2152/ETD-UT-2011-12-4580