A novel 10-bit hybrid ADC using flash and delay line architectures

A novel 10-bit hybrid ADC using flash and delay line architectures

This thesis describes the architecture and implementation of a novel 10-bit hybrid Analog to Digital Converter using Flash and Delay Line concepts. Flash ADCs employ power hungry comparators which increase the overall power consumption of a high resolution ADC. High resolution flash also requires pr...

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Bibliographic Details
Main Author:	Dutt, Samir
Format:	Others
Language:	English
Published:	2011
Subjects:	Hybrid 10-bit analog to digital converter Flash ADC Vernier delay line ADC Low power ADC Integrated circuits and systems
Online Access:	http://hdl.handle.net/2152/ETD-UT-2011-05-3585

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