Integration of virtual platform models into a system-level design framework

• Main Author: Salinas Bomfim, Pablo E.
• Format: Others
• Language: English
• Published: 2010
• Subjects: System level design; SLD; Virtual platforms; OVP; QEMU; Emulators; Instruction set simulator; ISS; EDA; SOC; SpecC; SystemC; System-on-chip
• Online Access: http://hdl.handle.net/2152/ETD-UT-2010-05-1257

The fields of System-On-Chip (SOC) and Embedded Systems Design have received a lot of attention in the last years. As part of an effort to increase productivity and reduce the time-to-market of new products, different approaches for Electronic System-Level Design frameworks have been proposed. These different methods promise a transparent co-design of hardware and software without having to focus on the final hardware/software split. In our work, we focused on enhancing the component database, modeling and synthesis capabilities of the System-On-Chip Environment (SCE). We investigated two different virtual platform emulators (QEMU and OVP) for integration into SCE. Based on a comparative analysis, we opted on integrating the Open Virtual Platforms (OVP) models and tested the enhanced SCE simulation, design and synthesis capabilities with a JPEG encoder application, which uses both custom hardware and software as part of the system. Our approach proves not only to provide fast functional verification support for designers (10+ times faster than cycle accurate models), but also to offer a good speed/accuracy relationship when compared against integration of cycle accurate or behavioral (host-compiled) models. === text