An improved method for register file verification
Register file logic verification historically involves comparing two human generated logic sources such as a VHDL code file and a circuit schematic for logic equivalence. This method is valid for most cases, however it does not account for instances when both logic sources are equivalent but incorr...
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| Format: | Others |
| Language: | English |
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2010
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| Online Access: | http://hdl.handle.net/2152/ETD-UT-2009-08-268 |