A C to Register Transfer Level Algorithm Using Structured Circuit Templates: A Case Study with Simulated Annealing
A tool flow is presented for deriving simulated annealing accelerator circuits on a field programmable gate array (FPGA) from C source code by exploring architecture solutions that conform to a preset template through scheduling and mapping algorithms. A case study carried out on simulated annealing...
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| Format: | Others |
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DigitalCommons@USU
2008
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| Online Access: | https://digitalcommons.usu.edu/etd/215 https://digitalcommons.usu.edu/cgi/viewcontent.cgi?article=1211&context=etd |