A Key Based Obfuscation and Anonymization of Behavior VHDL Models
Intellectual Property (IP) based Integrated Circuit (IC) design is an established approach for the design of a complex System-on-Chip (SoC). Porting the preparatory designs to third-party without enough security margin exposes an attacker to perform reverse engineering (RE) on the designs and hence...
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| Format: | Others |
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Scholar Commons
2018
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| Online Access: | https://scholarcommons.usf.edu/etd/7686 https://scholarcommons.usf.edu/cgi/viewcontent.cgi?article=8883&context=etd |
| Summary: | Intellectual Property (IP) based Integrated Circuit (IC) design is an established approach for the design of a complex System-on-Chip (SoC). Porting the preparatory designs to third-party without enough security margin exposes an attacker to perform reverse engineering (RE) on the designs and hence counterfeiting, IP theft etc., are common now-a-days. Design obfuscation can reduce RE attempt by an attacker. In this work, we propose a key based obfuscation and anonymization method for a behavioral IP. Given a behavioral VHDL description, the assignment and conditional statements are modified by incorporating random boolean operations with unique random key bits. The obfuscated VHDL is then anonymized by random identifiers. The resultant behavioral model can be simulated correctly upon application of original key sequence. Simulation results with nine datapath intensive benchmarks with three different lengths of test sequences show that the simulation overhead is negligible (only a few seconds). We evaluate the probability of reverse engineering the obfuscated design and show that it is extremely low. |
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