VHDL Coding Style Guidelines and Synthesis: A Comparative Approach

• Main Author: Inamdar, Shahabuddin L
• Format: Others
• Published: Scholar Commons 2004
• Subjects: Altera; Xilinx; Portability; FPGA; VHDL Subset; American Studies; Arts and Humanities
• Online Access: https://scholarcommons.usf.edu/etd/1089; https://scholarcommons.usf.edu/cgi/viewcontent.cgi?article=2088&context=etd

With the transistor density on an integrated circuit doubling every 18 months, Moore’s law seems likely to hold for another decade at least. This exponential growth in digital circuits has led to its increased complexity, better performance and is quickly getting less manageable for design engineers. To combat this complexity, CAD tools have been introduced and are still being continuously developed, which prove to be of great help in the digital industry. One of the technologies, that is rapidly evolving as an industry standard, is the Very High Speed Integrated Circuit Hardware Description Language, (VHDL), language. The VHDL standard language along with logic synthesis tools are used to implement complex digital systems in a timely manner. The increase in the number of specialist design consultants, with specific tools accompanied by their own libraries written in VHDL, makes it important for a designer to have an in-depth knowledge about the available synthesis tools and technologies in order to design a system in the most efficient and reliable manner. This research dealt with writing VHDL code in terms of hardware modeling, based on coding styles, in order to get optimum results. Furthermore, it dealt with the interpretation of VHDL code into equivalent optimized hardware implementations, which satisfy the constraints of a set of specifications. In order to obtain a better understanding of the different VHDL tools and their usefulness in different situations, a comparative analysis between Altera’s QuartusII and Xilinx’s ISE Webpack tools, was performed. The analysis compared their Graphics User Interface, VHDL Code Portability and VHDL Synthesis constraints. The analysis was performed by designing and implementing a screensaver circuit on an FPGA and displaying it on the VGA Monitor.