Performance Optimization in Three-Dimensional Programmable Logic Arrays (PLAs)
Increased chip size and reduced feature size has helped following Moores law for long decades. This has an impact on interconnect length, which is resulting in chip performance degradation. Despite the introduction of new materials with Low-K dielectrics for interconnects, their delay is expected to...
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| Format: | Others |
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Scholar Commons
2005
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| Online Access: | https://scholarcommons.usf.edu/etd/879 https://scholarcommons.usf.edu/cgi/viewcontent.cgi?article=1878&context=etd |