Performance Optimization in Three-Dimensional Programmable Logic Arrays (PLAs)
Increased chip size and reduced feature size has helped following Moores law for long decades. This has an impact on interconnect length, which is resulting in chip performance degradation. Despite the introduction of new materials with Low-K dielectrics for interconnects, their delay is expected to...
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| Format: | Others |
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Scholar Commons
2005
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| Online Access: | https://scholarcommons.usf.edu/etd/879 https://scholarcommons.usf.edu/cgi/viewcontent.cgi?article=1878&context=etd |
| Summary: | Increased chip size and reduced feature size has helped following Moores law for long decades. This has an impact on interconnect length, which is resulting in chip performance degradation. Despite the introduction of new materials with Low-K dielectrics for interconnects, their delay is expected to substantially limit the chip performance. To overcome this problem the need for new technology has arrived. One such promising technology is the three-dimensional Integrated chips (3D ICs) with multiple silicon layers.
In this thesis, three dimensional integrated chip (3D IC) technology has been implemented on programmable logic arrays (PLAs). The two-dimensional PLAs are converted to three-dimensional PLAs to realize the advantages of the third dimension. Two novel approaches for partitioning of PLAs are introduced for topological optimization. Greedy algorithm is implemented on the partitioned PLAs to utilize the third dimension for further enhancement in scalability factors. This concept has been implemented on MPLA (Magic Programmable Logic Array) tool.
The 3D PLA has been tested on MCNC91 benchmark suite and the results are presented. The experimental results are compared with the 2D-PLA on the same benchmark set. The results obtained indicate the efficacy of the proposed synthesis approach. |
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